The present invention relates, in general, to techniques for the integration of a high value capacitor with a ferroelectric memory on a common substrate. More particularly, the present invention relates to an integrated circuit and process for forming a relatively high value capacitance in an integrated circuit which additionally includes at least one ferroelectric memory device cell and does not require any additional processing steps to produce the high value capacitor.
Modern data processing systems require that a substantial portion of the information stored in its memory be randomly accessible to ensure rapid access to such information. Due to the high speed operation of memories implemented in semiconductor technologies, random access memories ("RAMs") have been developed in which a bit of binary information is stored in a single memory cell, which may comprise but a single transistor and associated capacitor, with a multiplicity of memory cells being grouped together into an array. Commonly available RAMs utilizing typical integrated circuit capacitor dielectrics include both dynamic RAMs ("DRAMs") and static RAMs ("SRAMs"). SRAMs utilize a memory cell structure which includes a number of transistors configured as a flip-flop, or a device having two stable states. The bi-stable states of the device then define either a logic level "one" or "zero." Because SRAM cells require a larger number of transistors than DRAMs, the amount of on-chip "real estate" needed for each individual cell is relatively large and it is, therefore, difficult to integrate such devices as densely. However, an inherent advantage of SRAMs over DRAMs is that they do not require refresh circuitry to continually restore the charge in the memory cell capacitor and they are capable of operating with extremely fast access speeds.
As previously mentioned, DRAM memory cells store data in a capacitor which is formed in the substrate of the integrated circuit semiconductor material. Because the logic level determined by the charge is stored in a capacitor and not in the current state of a bi-stable logic device, the charge tends to dissipate and therefore needs to be refreshed periodically in order to preserve the memory contents.
In conventional single transistor DRAM memory cells, the charge stored in the memory cell capacitor is selectively coupled through the source-drain path of an access transistor to the memory bit line. The access transistor then also has its gate electrode coupled to a word line. By turning on the access transistor, the charge stored in the capacitor is coupled through the source-drain path to the bit line where it is generally compared against another charge reference, such as a dummy memory cell or complementary bit line, in order that the state of the memory cell indicated by the charge stored in the capacitor may be determined.
With the increasingly higher level of integration of DRAM devices, since they generally comprise the aforementioned one transistor/one capacitor type, the individual memory cells must be decreased in size to the limits of available processing technology. This in turn, has the effect of ultimately reducing the available capacitance of the capacitor in the memory cell. Thus, one of the greatest difficulties in achieving higher integration of DRAM devices is to increase the charge storage capacity of the individual memory cell capacitors despite the reduction of the lateral dimensions of the capacitor to allow for the fabrication of such higher density memory arrays. Since capacitance is inversely proportional to the separation between the two capacitor plates and directly proportional to the dielectric constant, the capacitance increase may be accomplished by reducing the thickness of the dielectric (typically silicon dioxide or silicon nitride) separating the two plates or by increasing the dielectric strength. The dielectrics used in DRAMs have an already inherently low dielectric constant and are also limited in how thin they can be fabricated.
In fact, the dielectric constant of these typical dielectric materials is so low that they are also totally unsuited for use in fabricating relatively large value peripheral capacitive elements on the same substrate as the memory cell capacitors, as may be required in specific applications. Such large value capacitors would necessitate a device having physical dimensions consuming sufficient on-chip "real estate" to substantially preclude their integration, if the same IC process is used.
Capacitance is also directly related to the dielectric constant of the material between the capacitor plates. Therefore, even though it is theoretically possible to manufacture such a large value capacitor on the same substrate as a conventional memory device using a separate, relatively higher dielectric constant material, as a practical matter, it is extremely undesirable to add the additional processing steps and materials to the memory device process flow in order to provide such a capacitor. Such relatively high value peripheral capacitors are, nevertheless, most desirably integrated on a common substrate with the memory device, in order to obviate the requirement of using discrete, off-chip capacitors for the same function.
Ramtron International Corporation of Colorado Springs, Colo., assignee of the present invention, has pioneered the use of ferroelectric materials for use as the dielectric in memory cell capacitors. Ferroelectric materials exhibit an inherently high dielectric constant. RAMs using ferroelectric capacitors for memory cells, such as those utilized in Ramtron's FRAM.RTM. memory devices, also exhibit the significant advantage of being non-volatile. The non-volatility of ferroelectric RAMs is achieved by virtue of the fact that a ferroelectric capacitor includes a pair of capacitor plates with a ferroelectric material between them which has two different stable polarization states which can be defined with a hysteresis loop depicted by plotting the polarization against applied voltage. By measuring the charge which flows when a voltage is applied to a ferroelectric capacitor, the polarization state of the ferroelectric material can be determined. By arbitrarily assigning a logic level "zero" to one polarization state and a logic level "one" to the opposite polarization state, ferroelectric capacitors can be used to store binary information in a RAM memory array. The obvious advantage of a non-volatile memory is that data will continue to be stored within the memory cell even though power to the device may be interrupted or removed.
In accordance with the previously noted need for integrating a ferroelectric memory array with other associated circuitry on a common substrate, it is possible that a relatively high value peripheral capacitor, for example having a capacitance more than 100 to 100,000 times a typical memory cell capacitor such as for filtering supply voltages and the like, may be required. Utilizing conventional silicon dioxide and silicon nitride dielectric capacitors, the aforementioned inherent size constraints for fabricating such a relatively high value capacitor render integrating the same with a ferroelectric memory array prohibitive in terms of on-chip area and, as a consequence they must generally be furnished as discrete peripheral elements. Moreover, while ferroelectric capacitors have been utilized in a memory array cell, they have not heretofore been utilized to produce a linear integrated, high value peripheral capacitor for the integrated circuit.